1. Field of the Invention
The present invention relates to transmission and reception of signals between devices (nodes) attached to a computer over a serial bus such as the IEEE-1394 bus specified according to the IEEE-1394 Standard for a High Performance Serial Bus (or IEEE Std 1394-1995).
2. Description of the Related Art
The IEEE 1394 standard specifies protocols for the transmission and reception of various control signals and communication signals between peripheral devices of a computer such as printers, hard disk drives, scanners, digital cameras (nodes) at different layers of each node connected to a serial bus. For the physical layer of each node, a procedure is specified for bus initialization and determination of bus ownership. This procedure is described by a state machine having four broadly classified functions. The bus initialization procedure consists of three network initialization processes (Bus Reset process, Tree ID process, and Self ID process) and a Normal process (for normal communication between nodes).
For each of these processes a number of states are defined. For Bus Reset process, states R0 (Reset Start) and R1 (Reset Wait) are defined, and for Tree ID process states T0 (Tree ID start), T1 (Child Handshake), T2 (Parent Handshake) and T3 (Root Contention) are defined. Similarly, five states are defined for Self ID process, including S0 (Self ID Start), S1 (Self ID Grant), S2 (Self ID Receive), S3 (Send Speed Capabilities) and S4 (Self ID Transmit), and six states are defined for Normal process, including A0 (Idle), A1 (Request), A2 (Grant), TX (Transmit), RX (Receive) and PH (PHY Response). The present invention is primarily concerned with the operation of the Bus Reset process.
Two bus reset processes are defined by the IEEE-1394 standard (P1394a Draft Standard for a High Performance Serial Bus (Supplement), Draft 2.0 Mar. 15, 1998) long bus reset and short bus reset. The cable environment of the standard assumes that the state of the bus is unknown when a bus reset occurs and requires that a reset be long enough to permit all nodes of the bus to receive a long bus reset signal and perform longest transactions within a period of about 166 xcexcs. Short bus reset is a process in which a node that is performing a bus reset arbitrates for control of the bus prior to asserting reset. The duration of short bus reset is about 1.3 xcexcs.
In a bus reset process, the operation of a node proceeds according to FIG. 1. When a node detects a bus reset signal at one of its ports when powered on, or operating in a state other than state RX (=Receive) such as Tree ID, Self ID or Normal process, it changes to state R0 (=Reset Start) to begin a bus reset process and sets the reset time to the long reset time of 166 xcexcs. If the node is in state RX when it detects bus reset, it changes to state R0 and sets the reset time to the short reset time of 1.3 xcexcs.
In state R0, the node asserts a bus reset signal on all of its active ports. When the short reset time of 1.3 xcexcs expires the node changes to state R1 (=Reset Wait) in which all ports of the node return bus to idle state. If the node receives an idle or a parent notify signal from all of its active ports before the Reset Wait period of 1.46 ns expires, the state of the node changes to state T0 (=Tree ID Start) which is the initial state of Tree ID process. If all ports of the node receive no idle state signal nor parent notify signal within a period of 1.46 xcexcs (=the 1.3-xcexcshort reset time plus the 160-ns reset wait time) from state R1, the node returns from state R1 to state R0 and sets the reset time to the long reset time of 166 xcexcs.
In a short bus reset process that proceeds in a four-node network, for example (see FIG. 2A), a node 1 attempts to gain bus ownership prior to performing a bus reset by asserting a Request signal R(1) on one of the ports of a root node 2 that is authorised to assign bus ownership, changing its state from A0 (=Idle) to A1 (=Request). In response, the root node 2 returns a Grant signal G(2) to node 1 and asserts a Data Prefix signal D(2) on its other port, which is repeated by a node 3 as a Data Prefix signal D(3) to node 4. Nodes 3 and 4 change their state from A0 to RX. Node 1 responds to the Grant signal G(2) by changing its state from A1 to TX (=Transmit). Node 1FIG. 2B) changes to R0 (=Reset Start) by asserting a Data Prefix DP(4) followed by a Bus Reset signal and receiving a Bus Reset signal B(5) from the root node 2. The Data Prefix DP(4) and the following Bus Reset are repeated by root node 2 as D(5) which is repeated by node 3 as D(6) to node 4. Node 3 and 4 return Bus Reset signals B(6) and B(7) to nodes 2 and 3, respectively, and change their state from RX to R0 (=Reset Start) by setting reset time to the short reset time. When all nodes have changed their state to R1, nodes 1, 2, and 3 assert idle signals I(8), I(9) and I(10), respectively, to start a Tree ID process (FIG. 2C).
However, if the cable length between two nodes is longer than the 4.5 meter limit of the data-strobe link of the 1394 standard, there is a high likelihood of a bus reset signal from a node arriving on the node at the opposite end of the cable after expiration of the short reset time of 1.3 xcexcs, even if the source node is performing a short bus reset. Hence, the source node must perform a long bus reset. This is a serious problem for a bus environment in which internodal bus length is more than 50 meters by use of 8B/10B block coding and unshielded twisted pairs or fiber optic links (for further information, see P1394b Draft Standard for a High Performance Serial Bus (Supplement) Draft 0.17, Feb. 5, 1999).
Assume that the nodes 2 and 3 are interconnected by a long-distance cable as shown in FIG. 3 and that node 1 changes from A0 (=Idle) to A1 (=Request) by asserting a Request to node 2, which grants bus ownership and asserts a Data Prefix DP1 to node 3. Node 1 shifts to TX by asserting a Data Prefix DP2 and changes to state R0 by signalling a Bus Request BR1 to node 2, resulting in the node 2 changing to state R0 by simultaneously asserting a Bus Request BR2 to nodes 1 and 3. Node 3 changes its state from RX to R0 by signalling a Bus Request BR3 to nodes 2 and 4. When the short reset period of 1.3 xcexcs expires at node 2, it changes state from R0 to R1 by signalling an idle state ID2 to nodes 1 and 3. Similarly, the short reset time expires at node 2 and it changes from R0 to R1 by signaling an idle state ID3 to nodes 2 and 4. Root node 2 will change its state from R1 to R0 if the critical period of 1.46 xcexcs expires. Since an idle or a parent notify signal should arrive a 1.46-xcexcs period after the root node 2 changes to state R1 in order for it to reliably perform a short bus reset, the idle signal ID3 must arrive on node 2 within the 1.46-xcexcs critical period after the short reset period of 1.3 xcexcs. However, due to the long transmission delay between nodes 2 and 3, the idle state signal ID3 arrives on node 2 after the 1.46-xcexcs critical period and the node 2 changes to state R0, rather than T0, and sets the bus reset to the long reset time. In order for the node 2 to perform a short bus reset, an idle state or a parent notify state should arrive within a total period of 2.76 xcexcs after the node 2 asserted Bus Reset BR2 to node 3.
In a long-distance cable environment, the maximum turnaround time between two nodes is given by:
2xc3x971.3 xcexcs+0.16 xcexcs greater than 2 (cable delay+physical-layer delay)+1.3 xcexcs
therefore,
1.3 xcexcs+0.16 xcexcs greater than 2 (cable delay+physical-layer delay)
If the physical-layer delay is 300 xcexcs and the cable delay is 5 s/meter, the cable length between two nodes must not exceed 78 meters.
Additionally, in a data-strobe cable environment in which the internodal cable length is longer than 4.5 meters, use of a short reset time larger than the currently defined value of 1.3 xcexcs may be considered. However, nodes using the 1.3-xcexcs short reset time and those using a modified short reset time cannot properly be combined in a single network since there is an upper limit to the modified short reset time. For example, if the nodes 2 and 3 have different short reset times as shown in FIG. 4, it is necessary to satisfy the following relation:
2xc3x97(cable delay+physical-layer delay)+modified short reset time  less than 2.76 xcexcs
If the cable delay is 5 ns/meter and the physical layer delay is 144 ns, the modified short reset time must be smaller than 2.4 xcexcs. Therefore, in a data-strobe cable environment, there is an upper limit on the internodal cable length.
It is therefore an object of the present invention to provide a transceiver circuit and method for reliably performing a short bus reset in a cable environment in which the internodal cable length is longer than 4.5 meters in the case of data-strobe links or longer than 78 meters in the case of long-distance links using a signalling scheme such as 8B/10B block codes.
According to a first aspect of the present invention, there is provided a transceiver circuit comprising a line transmitter for transmitting a signal from a higher layer to a transmission medium, a line receiver for receiving a signal from the transmission medium, a first detector for producing a first detector output if a first bus reset signal is detected in the signal transmitted from the line transmitter, and a second detector for producing a second detector output when the second bus reset signal is being detected in the received signal Control circuitry is provided for normally applying the received signal to the higher layer. A selector is provided having a first position in which the selector is normally coupling the received signals to the higher layer and a second position in which the selector is coupling a masking signal to the higher layer. Control circuitry sets the selector in the second position in response to a start timing of the first detector output, starts a count operation for incrementing a count value in response to a start timing of the second detector output until the count value exceeds a predetermined value, and sets the selector in the first position in response to the end timing of the count operation.
According to a second aspect, the present invention provides a method of performing a bus reset process, comprising the steps of (a) transmitting a signal to a transmission medium and receiving a signal therefrom, (b) applying the received signal to a higher layer, (c) detecting a transmit bus reset signal in said transmitted signal, (d) exclusively applying a masking signal to said higher layer in response to a start timing of the transmit bus reset signal, (e) detecting a receive bus reset signal in the received signal, (f) activating a count operation for incrementing a count value in response to a start timing of the receive bus reset signal until the count value exceeds a predetermined value, and (g) exclusively applying the received signal to said higher layer in response to an end timing of the count operation.